Hardware

CXL (Compute Express Link)

CXL (Compute Express Link) is an open industry-standard interconnect built on PCIe physical and electrical layers that enables coherent, high-bandwidth, low-latency connections between CPUs, GPUs, memory, and storage devices. CXL memory expansion and persistent memory devices complement NVMe storage by adding byte-addressable, non-volatile capacity accessible at near-DRAM latency.

NVMe Storage

CXL Protocol Layers

CXL 3.0 defines three protocol sub-types that can be used simultaneously over the same PCIe physical link:

  • CXL.io — Standard PCIe-compatible I/O. All CXL devices support this.
  • CXL.cache — Enables devices (accelerators, FPGAs) to coherently cache host memory without software mediation.
  • CXL.mem — Allows the host to access device-attached memory (DRAM or persistent memory) as a coherent memory pool.

CXL and NVMe Storage

CXL and NVMe address different tiers in the storage hierarchy. NVMe SSDs sit in the block storage tier (50µs+ latency, TB capacity). CXL memory expanders target the memory tier (nanosecond latency, GB–TB capacity) — filling the gap between DRAM and NVMe with persistent or volatile memory at lower cost per GB than DRAM.

In a future tiered architecture:

  • DRAM — Active working set (~nanoseconds)
  • CXL persistent memory — Extended memory / hot data tier (~100ns)
  • Local NVMe SSD — Warm data (~10µs)
  • Disaggregated NVMe-oF — Shared storage pool (~30µs)
  • Object storage — Cold / archival (seconds)